Integrated circuits (ICs) are typically manufactured with external connections for receiving either power supply, control or communication connections with external devices or systems. The trend in fabricating ICs is to increase the density of internal components, such as transistors and interconnects. In addition, the power supply potential used to operate the integrated circuits continues to decrease.
As integrated circuit devices increase in density and operating supply voltages decrease, the integrated circuits become more sensitive to the effects of electrostatic discharge. Electrostatic discharge (ESD) refers to the phenomenon of electrical discharge of high current for a short time duration resulting from a build up of static charge on a particular integrated circuit package, or on a nearby human handling that particular IC package. ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire IC. Because ESD events occur often across the silicon circuits attached to IC package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits.
One solution is the use of a grounded gate transistor as a simple ESD protection circuit. The transistor is configured as a diode and has a drain junction breakdown voltage lower than the gate dielectric breakdown voltage. While this circuit provides some protection from ESD events, it cannot pass the large currents inherent to some ESD events. An ESD protection circuit should be able to protect an IC against any conceivable static discharge by non-destructively passing large currents through a low impedance path in a short time.
One difficulty in designing ESD protection circuits is the demanding performance requirements that must be met. For example, one of the primary industry standards for measuring ESD robustness (MIL-STD-883C method 3015.7 Notice S (1989), and its follow-on Human Body Model (HBM) standard No. 5.1 (1993) from the EOS/ESD Association) requires ESD testing on a large number of pin and power supply combinations. In the past, ESD protection circuits have had difficulty meeting these stringent requirements while maintaining adequate noise immunity.
Integrated circuits have come under pressure in HBM tests because of repeated stressing of the power supply rails, leading to wear out of various breakdown points, such as an upper voltage supply, Vcc, line. A reliable power supply clamp is needed to reduce the susceptibility of the Vcc bus to failure mechanisms related to ESD testing. Further, ESD protection of input and output pins becomes simpler with a reliable power supply clamp because ESD current can be routed to one supply or another.
A p-channel field effect transistor (PFET) power supply clamp is described in U.S. patent application Ser. No. 08/823,109, filed Mar. 24, 1997 entitled "MOSFET-based Power Supply Clamps for Electrostatic Discharge Protection of Integrated Circuits." This clamp circuit uses a PFET to provide a discharge path through the transistor for the electrostatic voltage. A gate of the transistor is pulled close to ground during an ESD event. A threshold drop, therefore, is experienced across the transistor. Thus, the transistor does not dissipate the maximum possible current from the supply node.
For the reasons stated above, there is a need in the art for a circuit which increases the area efficiency of ESD power supply clamping circuitry to sink larger currents during an ESD event.